Computers rely on random access memory to store program instructions and data. Computer memories are made up of memory cells, where each cell stores a single bit of data. Each computerized instruction and/or computerized element of data typically comprises a set of bits meaningfully organized into a simultaneously addressable collection of bits such as a byte (generally 8 bits), a word (generally a multiple of bytes), a block (generally a multiple of words), etc. The position of a bit within a given byte, word, block, etc. (hereinafter referred to collectively as “bytes”) is meaningful in that meaning is given to bytes of data or instructions according to the values of the bits as positioned within the bytes according to a predefined ordered format.
Bytes and words are therefore typically addressed as a single entity using an address bus, a data bus, and memory cell enablement circuitry. More particularly, an address is placed on the address bus, cells of the memory device are enabled by activating write or read enable lines corresponding to the addressed cells, and data is either written to the cells or read from the cells addressed by the address bus, depending on whether the operation is a write operation or a read operation.
To keep up with the demand for faster and more capable systems, modern memory devices such as random access memories (or RAMs), Static RAMs (SRAMs), etc., are very dense. Because of their density, and the limitations of the manufacturing process, semiconductor memory devices will often contain one or more defective memory cells immediately after manufacture.
During the manufacturing and testing of a memory device, memory testing is performed in which all of the memory cells of the memory device are tested. Typical tests include sequentially incrementing or decrementing memory addresses while writing 0's and 1's into the memory cells. It is customary to refer to a collection of 1's and 0's being simultaneously written to or read from during a memory cycle as a “vector”, while the term “pattern” refers to a sequence of vectors. It is conventional for tests to include writing patterns into the memory space such as checkerboards, walking 1's and butterfly patterns.
As mentioned previously, individual memory cells may fail during test. To improve the yield of these devices, manufacturers typically incorporate redundant memory cell groups such as redundant rows and/or redundant columns of cells. It is often possible to substitute the redundant memory cell groups in place of corresponding memory cell groups in the memory device that contain one or more defective memory cells, thereby yielding a fully functional memory device. The redundant memory cell groups may be mapped into the memory device to replace memory cell groups in the memory device that have one or more memory cell failures. The process of identifying defective memory cell groups that contain failing memory cells and mapping redundant memory cell groups to corresponding defective memory cell groups in the memory device is called “redundancy analysis”.
Typically, a single given memory cell is a member of multiple different memory cell groups and therefore may be repaired using one of multiple different available redundant memory cell groups. For example, the memory device may be organized into rows and columns, allowing for memory cell groups that comprise rows and memory cell groups that comprise columns. The memory device may provide a number of redundant rows and a number of redundant columns that may be mapped to replace various rows and columns in the memory device. In this example, there may be available both a redundant row and a redundant column, either of which could be used to repair the given cell. If there are multiple failures along the same row, then it is better to use a single redundant row to repair the multiple memory cell failures rather than to use several redundant columns since it would be more efficient and only a limited number of redundant memory rows and columns are available. Suppose, for instance, that there are only four redundant columns and four redundant rows available to repair defective memory cells in a given memory device. In this example, if there is a row that has failures at three different columns, that row can be repaired either by using three of the redundant columns, or by using just one of the redundant rows. If, however, there is a row that has failures at five different columns, then that row can only be repaired by making use of one of the redundant rows since there are not enough redundant columns available to repair all of the failures in this row. A row that can only be repaired using one of the available redundant rows is considered a “must repair” row. Similarly, a column that can only be repaired using one of the available redundant columns is considered a “must repair” column.
It is known that once a given row or column has been identified as a “must repair” row or column, respectively, due to detection of a minimum number of memory cell failures in that row or column, all of the memory cell failures in the given row or column will be repaired by an available redundant row or column, respectively, so that it is unnecessary to further test or analyze any remaining untested memory cells in the given row or column of the memory device for failures.
How repair of defective memory cells using redundant memory cell groups is actually achieved on the circuit level is well understood by those who manufacture such devices, so it is sufficient for those skilled in the art to simply say that incorporated into those devices are some number of selectably destroyable elements whose destruction enables gating that in turn alters the internal logic of an associated circuit. This ability is used to route internal signals to replacement circuits that substitute for defective ones.
Ideally, a memory tester should be able to identify a need for repair in the memory device under test, the location of the required repairs, and the type of repairs needed, and then must be able to perform the appropriate repairs.
In certain memory testers, hardware may be designed to capture an entire bitmap, herein referred to as an error image, of the device contents. The error image is addressed by the same address as, or by an address derived from, the address that is applied to the memory device under test. During a test, when the contents of a memory cell in the memory device matches or fails to match expected results, a corresponding bit at that address in the error image is either set or cleared, according to the convention in use. For example, a zero (“0”) may be used to represent a failure to match and a one (“1”) may be used to represent a match. The error image may be analyzed to find the errors and the optimum solution. This strategy significantly reduces the complexity of the analysis task, as well as reducing test time.
Often, multiple “tag” images are generated during the testing of the memory device. The tag images map memory cell failures detected in the memory device over a single dimension. In the example above, one tag may contain a map of failing rows, and another may contain a map of failing columns. Within the row tag, one location may contain a flag indicating whether there were any errors in any of the memory cells in the corresponding row of the memory device. Similarly, within the column tag, one location may contain a flag indicating whether there were any errors in any of the memory cells in the corresponding column of the memory device. Because in the tag images a single memory location (typically only a bit in size) is used to represent an entire row or column of the memory device, a tag image is substantially smaller than the a full error image, which makes it possible to quickly identify which memory cell groups (in the above example, which rows and columns) have failures. The tag images thus operate to store an indexed collection of detected events for later inspection.
FIG. 1 is a block diagram of a conventional system for testing a memory device. A memory tester 4 applies a series of test vectors 3 to a memory device under test (DUT) 2 to detect failures in any of the memory cells of the memory DUT 2. The DUT 2 includes an array of memory cells 2a arranged in memory cell groups of rows ([0 . . . X−1]) and memory cell groups of columns ([0 . . . Y−1]). Traditionally, an error image 6 of the same size (row, column) as, and addressable in the same way as, the memory device under test (DUT) 2 is provided to store a bit corresponding to each memory cell of the memory DUT 2. Conventionally, a value of 0 in a bit cell of the error image 6 indicates that a failure occurred during testing of the corresponding bit cell 2a in the memory DUT 2, while a 1 indicates that no failure was detected in the corresponding bit cell 2a in the memory DUT 2. Of course, other conventions may be used to indicate the pass or fail of corresponding bit cells in the memory DUT 2.
A set of redundant memory cell groups of rows 8 ([0 . . . M−1]) and a set redundant memory cell groups of columns 10 ([0 . . . N−1]) may be implemented for use in repairing failures detected in memory cells 2a of the DUT 2 addressed by corresponding row and column addresses.
Traditionally, row and column tag images 14, 12 implement a single bit per address in the corresponding row or column direction to indicate the existence of at least one failure somewhere along the corresponding row or column of the DUT 2. Tag images may assist in performing analysis of the error image to determine how to repair any detected failures in the memory DUT.
As an illustrative example, consider that an address applied to the DUT 2 might be separable into row and column dimensions with corresponding row X and column Y address components that relate to the internal organization of the memory DUT 2. The memory DUT 2 is therefore addressable in two dimensions and the address applied to the DUT 2 has the X and Y address components embedded therein, but perhaps not in an obvious or convenient way. Suitable gating circuits can extract, for example, the Y address component and apply it as an address to a column tag image 12, which allows storage of information that is indexed according to the Y address. Similarly, gating circuits can extract the X address component and apply it as an address to a row tag image 14, which allows storage of information that is indexed according to the X address. Traditionally, the information stored in each entry of the row and column tag images is a single bit whose end-of-test meaning is that a failure did or did not occur at least once in the DUT 2 along the corresponding respective X addressed row or Y addressed column. By generating tag images for both row X and column Y address components, a test analyzer can obtain useful information about the failures in a memory DUT whose internal organization includes the notions of row X and column Y addresses. The use of tag images 12, 14 may realize a significant reduction in tester memory requirements as the needed tag image storage requirements consist of a number of locations equal to only the sum of the X and Y address spaces, rather than equal to their product, which is what a conventional error image would have to have.
A common failure mechanism of memory devices reduces the effectiveness of conventional tag images. Many times devices have a stuck group of memory cells in which many or all addresses within that particular memory cell group are defective. For example, in the memory DUT 2 of FIG. 1, testing may reveal that the DUT 2 has a stuck row or a stuck column in which many or all addresses within that particular stuck row or a stuck column are defective. A single redundant memory cell group may repair the stuck memory cell group in the memory device. However, in devices that are organized in memory cell groups in multiple dimensions so that a given address applied to the memory device includes multiple dimensional address components embedded therein, the tag images may be rendered ineffective for purposes of redundancy analysis, as best understood from the following example. Again referring to DUT 2 of FIG. 1, which is organized into memory cell groups (rows 0 . . . X−1 and columns 0 . . . Y−1) in two dimensions (a row dimension and a column dimension), a single redundant row may repair a stuck row in the DUT 2. However, the column tag 12 may indicate a failure in all Y addresses due to the failures in all memory cells of the stuck row of the DUT 2. If the memory DUT 2 has both a stuck row and a stuck column, then both tag images 12 and 14 may indicate complete failures in all addresses, whereas in actuality it may be merely that all X addresses within a single column and all Y addresses within a single row are defective. In devices that have stuck row or stuck column failures, the usefulness of the tag images may therefore be limited or even rendered completely ineffective insofar as extracting information concerning rows and/or columns containing only sparse failures.
Accordingly, there exists a need in the art for a technique for improving and streamlining redundancy analysis in memory test and thus to reduce the test time and hardware needed for testing of memories. There also exists a need to improve the effectiveness and usability of tag images in memory devices having stuck rows and/or stuck columns.